Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits (“ICs”) are ongoing goals of the computer industry. As new generations of IC products are released, the number of devices used to fabricate them tends to decrease due to advances in technology. Simultaneously, the functionality of these products increases. For example, on the average there is approximately a 10 percent decrease in components for every product generation over the previous generation with equivalent functionality.
In IC packaging, in addition to component reduction, surface mount technology (“SMT”) has demonstrated an increase in semiconductor chip density on a single substrate despite the reduction in the number of components. SMT is a method used to connect packaged dies to substrates. With SMT, no through-holes in the board are required. Instead, package leads are soldered directly to the board surface. This results in more compact designs and form factors, and a significant increase in IC density and performance. However, despite these reductions in size, IC density continues to be limited by the space or “real estate” available for mounting dies on a substrate, such as a printed circuit board (“PCB”).
One method to further increase IC density is to stack semiconductor dies vertically. Multiple stacked dies can be combined into a single package in this manner with a very small surface area or “footprint” on the substrate or PCB. In many cases, however, this requires customized die configurations. In these and other cases, passive devices (resistors, capacitors, etc.) that are associated with the dies are still variously mounted to the substrate usually around the peripheries of the dies, thus continuing to occupy valuable real estate.
Therefore, it would be advantageous to develop a stacking solution and assembly configuration for increasing IC density using non-customized (i.e., standard) die configurations with commercially-available, widely-practiced semiconductor device fabrication techniques. This is ever more critical as the semiconductor industry continues to demand semiconductor devices with lower costs, higher performance, increased miniaturization, and greater packaging densities. Substantially improved system-in-package (“SiP”) solutions are greatly needed to address these requirements.
Typically, a SiP is assembled in a multichip module (“MCM”) format, with multiple passive components mounted at the periphery of the semiconductor die. However, while stacked die packaging technologies have made it possible to even further reduce the substrate size for die attachment, the area for passive component attachment with SMT still needs to be reserved substantially at the top surface of the substrate. This greatly restricts and limits the potential for miniaturization that stacked die packaging might otherwise afford. The limitations are exacerbated by such peripheral placement of the passive components around the active components that are more in the center.
Thus, a need still remains for SiP systems that are capable of compactly integrating a plurality of passive components in combination with active components to achieve an optimal high-density small footprint for such composite semiconductor SiP systems. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions, and thus, solutions to these problems have long eluded those skilled in the art.